1. Technical Field
Various embodiments generally relate to a semiconductor chip, a stack chip including the same and a testing method thereof, and more particularly, to a technology for testing a fail of a bump in a stack chip.
2. Related Art
As the development of the electronics industry rapidly proceeds, light weight, scale-down, high speed operation, multi-functionality and high performance are demanded by users. One of the electronic product assembly technologies developed according to such demands is a chip scale package or a chip size package.
The chip scale package may significantly reduce the thickness or size of a semiconductor or a system-on-chip package. In the case where a semiconductor device or system-on-chips of the chip scale package are stacked, micro bumps may be disposed to ease the physical contact between stacked chips.
In a conventional memory device, an input/output buffer is directly electrically coupled to a bonding pad. That is to say, in a chip where bonding is performed, a wafer test is performed through a bonding pad. Accordingly, by directly performing a probe test through a bonding pad before performing wire bonding, input leakage current of an input/output buffer may be tested. In particular, a test for input leakage current through a bonding pad may be directly performed among various test items.
As a stack memory is developed, a memory to be directly stacked on a system-on-chip has a structure which is electrically coupled with the underlying system-on-chip not through wire bonding but through micro bumps.
In the memory having such a structure, because input/output buffers are electrically coupled to the micro bumps, it is impossible to perform a probe test by directing contacting the micro bumps. In other words, in a memory using TSVs (through-silicon vias) and micro bump pads as a new memory type, it is impossible to perform a test by directly probing micro bumps.
Even though a probe test is directly performed for micro bumps, a micro bump which is contaminated after the test is not likely to be electrically coupled well when stacking a system-on-chip. Namely, in the case of directly probing micro bumps, the shapes of the micro bumps may be changed attributable to attacks by probe pins.
According to this fact, when stacking is performed using a bump which is contaminated after testing, various fails such as an open circuit or a short circuit are likely to occur. As a consequence, if leakage current occurs in a bump or an input/output buffer electrically coupled with the bump, it is not easy to find the leakage current.